A magnetic random access memory (MRAM) capable of high-speed write and read operations is a non-volatile memory which can perform a number of rewrite operations, and is expected as a memory substituted for an existing DRAM or SRAM.
As one of the MRAMs, U.S. Pat. No. 6,545,906 discloses a toggle MRAM. In the toggle MRAM, a magnetic tunneling junction (MTJ) is used as a storage element, in which a laminated free layer is used. This toggle MRAM differs from the conventional typical MRAM in a memory cell structure and a write operation principle, and is particularly superior in a selection property of the memory cell in the write operation.
As described in U.S. Pat. No. 6,545,906, the MTJ structure used in the toggle MRAM is such that a first free layer and a second free layer, which are equal in film thickness, are laminated through a non-magnetic metal layer. A pinned layer and a reference layer under the free layer are also laminated through a non-magnetic metal layer. The magnetization directions of the pinned layer and the reference layer are strongly fixed when they are manufactured. The directions of a first free layer magnetization of the first free layer and a second free layer magnetization of the second free layer can be changed, for example, by magnetic fields generated by the write currents flowing through a write bit line and a write word line. Here, the first and second free layer magnetizations are stable in an anti-parallel state in which they are inverse to each other at 180 degrees.
FIG. 1 shows a planar layout of the memory cell in the toggle MRAM described in U.S. Pat. No. 6,545,906. The planar layout of the memory cell in the toggle MRAM differs from that of the conventional typical MRAM. In the toggle MRAM, a magnetization easy axis direction of a MTJ 125 is arranged, for example, at a direction inclined at about 45 degrees from an X-direction in which a write word line 123 extends and a Y-direction in which a write bit line 121 extends. This is intended to simplify a toggle operation, which will be described later.
The sensing operation principle of the toggle MRAM is similar to the sensing operation principle of the conventional typical MRAM. However, the write operation principle of the toggle MRAM differs from the conventional typical MRAM. The write operation principle of the toggle MRAM will be described below. The write operation of the toggle MRAM disclosed in U.S. Pat. No. 6,545,906 executes in advance the sensing of a selected memory cell. Then, its sensing result and a data to be written are compared, and if they correspond to each other, the write operation is not executed, and if they are not corresponds to each other, the write operation is executed. The write operation is executed by changing the first and second free layer magnetizations (executing the toggle operation).
FIGS. 2 to 4 are views showing the toggle operation principle of the conventional toggle MRAM. In the toggle operation, as shown in FIG. 2, a write current IWL is supplied to the write word line 123 at a time t1, and a write current IBL is supplied to the write bit line 121 at a time t2. Moreover, at a time t3, the write current IWL is stopped, and at a time t4, the write current IBL is stopped. With the series of the current controls, a rotational magnetic field is applied to the intersection between the write word line in a selection state to which the write current IWL is supplied and the write bit line in a selection state to which the write current IBL is supplied. In association with this, each of the first and second free layer magnetizations of the MTJ is rotated (the toggle operation is carried out) in a spin flop state. That is, as shown in FIG. 3, in a case that an initial state is a [0] state, it is rewritten (toggled) to a [1] state. As shown in FIG. 4, in the case of the [1] state, it is rewritten (toggled) to the [0] state. In the toggle MRAM, only one directional magnetic field is applied to memory cells in a half-selection state that is arranged on the write word line 123 in the selection state or on the write bit line 121 in the selection state. Thus, a possibility of an erroneous writing is very low. Hence, it is not required to strictly control the write current value, which dramatically improves the write margin, as compared with the conventional typical MRAM.
In a typical clock synchronous RAM, a burst operation is prepared in specifications. This is the technique that automatically changes an inner burst address in synchronization with a clock and consequently attains high-speed read and write operations. In particular, in a continuous burst operation in the specifications, all of column addresses including the bust address are changed and operated synchronously with the clock. FIG. 5 is a view showing a timing chart of a continuous burst read operation. Here, (a) indicates a clock signal, (b) indicates an address signal, (c) indicates an address advance signal, (d) indicates an output enable signal, (e) indicates a write enable signal, (f) indicates a column address signal, (g) indicates a burst address signal, and (h) indicates a signal inputted/outputted through input/output pins, respectively. In this continuous burst read operation, the sensing results of the memory cells corresponding to all of the column addresses are sequentially outputted synchronously with the clock.
FIG. 6 is a view showing a timing chart of a continuous burst write operation. Here, (a) indicates a clock signal, (b) indicates an address signal, (c) indicates an address advance signal, (d) indicates an output enable signal, (e) indicates a write enable signal, (f) indicates a signal inputted/outputted through input/output pins, (g) indicates a column address signal, (h) indicates a burst address signal, and (i) indicates a write data signal, respectively. In this continuous burst write operation, the write data inputted synchronously with the clock are sequentially written to the memory cells corresponding to all of the column addresses including the burst address.
Here, the write operation of the typical MRAM can control the free layer magnetization of the MTJ element, depending on the direction of the write current corresponding to the write data. Thus, the existing RAM technique can be applied in its original state to similarly execute the continuous burst write operation.
However, the write operation of the toggle MRAM is executed, depending on whether or not the free layer magnetization is inverted (toggle-operated). For this reason, prior to the toggle operation, in order to determine whether or not the toggle operation is executed, it is required to sense the state of the memory cell. This fact causes the execution of the continuous burst write operation of the toggle MRAM to be very difficult. For example, if the sensing operations of the memory cells corresponding to the all column addresses are executed in the period until the start of the burst write operation after the input of the addresses, it is possible to execute the continuous burst write operation even in the toggle MRAM. However, all of the bit lines require the sense amplifier. Thus, this is impractical because a circuit area is explosively increased. Also, when the sense amplifiers whose number is fewer than that of the bit lines are used to cope with all of the column addresses, the sensing operations for different memory cells are required to be executed simultaneously with the burst write operation.
FIG. 7 is a view showing an example of a timing chart of the continuous burst write operation in the toggle MRAM. Here, (a) indicates a clock signal CLK, (b) indicates an address signal Address, (c) indicates an address advance signal /ADV, (d) indicates an output enable signal /OE, (e) indicates a write enable signal /WE, (f) indicates a signal Din inputted/outputted through input/output pins, (g) indicates a row address signal RA, (h) indicates a burst address signal BA, (i) indicates a read column address signal RCA, (j) indicates a read enable signal RE, (k) indicates a sense amplifier output signal Qout, (l) indicates a write column address signal WCA, (m) indicates an inner write enable signal WE, (n) indicates a write current (Ix), and (o) indicates a write current (Iy), respectively.
This continuous burst write operation separates the column address into the two systems for the sensing operation and the write operation. That is, the column address is separated into the (i) read column address signal RCA for selecting only the memory cell to which the sensing operation is possible and the (l) write column address signal WCA for selecting only the memory cell to which the write operation is possible. The WCA signal is outputted while having a delay (latency) of several clocks behind the RCA signal. FIG. 7 exemplifies a case of a latency=2 (clocks).
In FIG. 7, the following operations are executed at the respective cycles of the CLK signal after the address signal is supplied.
(1) From 0th to 1st Cycles
A sensing operation A is executed for memory cells A which are located at a column address of 0 and burst addresses of 0 to 7 (the (i) RCA signal, the (j) RE signal).
(2) From 2nd to 9th Cycles
These sensing results of the memory cells A and the data input signal inputted from outside are used to execute the burst write operation (the (k) Qout signal, the (f) Din signal, the (e)/WE signal, the (h) BA signal, the (l) WCA signal, the (m) WE signal, the (n) Ix signal and the (o) Iy signal).
(3) From 8th to 9th Cycles
A sensing operation B for memory cells B which are located at a column address of 0 and burst addresses of 0 to 7 is executed (the (i) RCA signal, the (j) RE signal).
(4) From 10th to 17th Cycles
The sensing result of the memory cells B and the data input signal inputted from outside are used to execute the burst write operation (the (k) Qout signal, the (f) Din signal, the (e)/WE signal, the (h) BA signal, the (l) WCA signal, the (m) WE signal, the (n) Ix signal and the (o) Iy signal).
The subsequent operations will be similarly executed.
FIG. 8 is a view showing a situation of a memory array at the 9th cycle of the CLK signal in FIG. 7.
The write currents Ix, Iy flow through the write word line 123 and the write bit line 121, respectively, in the memory cell A which is located at the column address of 0 (the (l) WCA signal) and the burst address (the (h) BA signal) of 7, respectively. At the same time, the sensing operation of the memory cell B which is located at the column address of 1 ((i) the RCA signal) is executed. At this time, the write current Ix flows through the write word line 123 of the memory cell B. Thus, the magnetization of the memory cell B is in the unstable state (the spin-flop state) that is neither at [0] nor at [1]. Thus, the data stored in the memory cell B cannot be rightly sensed. In this way, since there is the cycle in which the sensing operation and the write operation are executed at the same time, it is difficult to execute the continuous burst write operation.
If the sensing operation is executed for each clock cycle, there is a possibility that the foregoing problems can be solved. However, in that case, it is difficult to make a clock frequency high. This results in the drop in the speed of the write operation. If so, the merit of the execution of the continuous burst write operation is lost.
As the related art, Japanese Laid-Open Patent Application (JP-P 2003-77267A) discloses a thin film magnetic substance storage device. This thin film magnetic substance storage device includes a memory array including a plurality of memory cells that are arranged in a matrix shape. The electric resistance of each of the memory cells is changed in accordance with the storage data that is magnetically written by first and second data write currents. This includes a plurality of write digit lines, a plurality of write bit lines, a plurality of word lines, and a column selecting unit. Each of the plurality of write digit lines is provided correspondingly to each of memory cell columns, and when they are active, the first data write current is supplied to a column direction. Each of the plurality of write bit lines is provided correspondingly to each of memory cell rows, and when they are active, the second data write current is supplied to the row direction. Each of the plurality of word lines is provided correspondingly to each of the memory cell columns, and the selection column including the selection memory cell selected as a data read target is active. The column selecting unit executes the column selection in the memory array. The column selecting unit executes the column selection in the memory array. The column selecting unit includes a column decoding circuit, a word line selecting circuit and a write digit line selecting circuit. The column decoding circuit decodes a column address. The word line selecting circuit is provided correspondingly to each word line, and activates the corresponding word line, in accordance with the decoded result of the corresponding memory cell column, when the data is read. The write digit line selecting circuit is provided correspondingly to each of the write digit lines and activates the corresponding write digit line, in accordance with the decoded result of the corresponding memory cell column, when the data is written.
Japanese Laid-Open Patent Application (JP-P 2004-530240A) discloses a MRAM architecture and system. This magnetic resistance memory is formed on a common substrate. The magnetic resistance memory is provided with first and second magnetic resistance memory arrays, a plurality of word/digit lines, a switching circuit and a current source. The first and second magnetic resistance memory arrays are provided on the substrate, separately from each other, and each of them has a plurality of magnetic resistance memory cells arranged in a plurality of columns and rows. Each of the plurality of word/digit lines is magnetically coupled to the magnetic memory cell on each column in each of the first and second magnetic resistance memory arrays. The switching circuit is provided between the first and second magnetic resistance memory arrays on the substrate and designed to select the word/digit line in the magnetic resistance memory cell on any or one of the first and second magnetic resistance memory arrays. The current source is provided adjacently to the switching circuit on the substrate and connected to the switching circuit, in order to supply the write current to the selected word/digit line in the magnetic resistance memory cell on the column.